Computing Hardware — From von Neumann to CPU, GPU, FPGA, and ASIC

CPU, GPU, FPGA, and ASIC are not four generations in which each new device replaced the previous one. A CPU handles complex control and broad software, a GPU drives high throughput across many similar operations, an FPGA reconfigures circuits in the field, and an ASIC fixes circuitry around a narrow task. Modern systems combine them with controllers, networks, and storage.

At least six axes matter: the switching medium (relay, vacuum tube, transistor), integration onto a chip, ISA and software compatibility, circuit reprogrammability, granularity of parallelism, and the institutions that design, manufacture, and operate the machine. Transistor count, clock, core count, FLOPS, and hashes per second cannot form one universal ranking.

Here ASIC is an operational term for an integrated circuit whose logical function is not reconfigured in the field and is optimized for a domain. In a broader sense CPUs and GPUs are also application-oriented ICs; the narrower usage lets us distinguish general processors, reconfigurable logic, and fixed-function accelerators.

In 1945, the First Draft of a Report on the EDVAC, issued under John von Neumann’s name, described functional organs for arithmetic, central control, memory, input, and output. It widely circulated a logical design in which instructions and data could be represented as numbers in electronic memory—an important document in what later became known as “von Neumann architecture.”

But von Neumann did not invent the stored-program computer alone. The First Draft grew from the Moore School collaboration around ENIAC and EDVAC, including J. Presper Eckert, John Mauchly, Herman Goldstine, and others. A single name on a report and attribution of the underlying invention are different historical questions.

“Stored program” is itself a later historian’s category, absent from the contemporary report. Reducing rewiring, executing from writable memory, sharing memory between instructions and data, and the modern code model are related but not identical claims. Any “world first” must therefore define what it is counting across the Manchester Baby, converted ENIAC, EDSAC, and other machines.

Vacuum-tube machines at ENIAC scale operated electronically but demanded many tubes, substantial power and cooling, large wiring spaces, and constant maintenance. In December 1947, John Bardeen and Walter Brattain demonstrated amplification in a germanium point-contact transistor at Bell Labs. William Shockley led the research group and later conceived the junction transistor. Their distinct contributions should not be collapsed into one inventor.

Jack Kilby at Texas Instruments in 1958 and Robert Noyce at Fairchild Semiconductor in 1959 independently opened paths to the integrated circuit. Kilby’s monolithic idea and Noyce’s combination of planar processing with metal interconnect made different contributions. In 1960, Mohamed Atalla and Dawon Kahng demonstrated the MOS transistor at Bell Labs, creating a foundation for dense digital circuits.

Integration was not just miniaturization. Shorter wires, fewer connection points, repeatable photolithography, many dies per wafer, packaging, testing, and manufacturing yield made complex processors reproducible at scale. Today’s process-node labels in nanometres are not a literal measurement of one universal physical feature.

The Intel 4004 grew from Busicom’s calculator project and was commercialized in 1971 as a 4-bit CPU by a team including Federico Faggin, Ted Hoff, Stanley Mazor, and Masatoshi Shima. It is central to the history of early commercial single-chip microprocessors, but definitions that include the AL1, MP944, or multi-chip designs change the answer to “first.” Intel did not invent the abstract CPU, and no single person built the 4004 alone.

Processor history is also ISA history. IBM System/360 demonstrated a compatible computer family in 1964. The x86 line from Intel’s 8086 carried a large software inheritance, and AMD64 extended x86 to 64 bits while preserving a path for 32-bit software. RISC research and Arm opened other implementation choices. Arm long centred its business on licensing architectures, processor IP, and compute subsystems, then announced its first Arm-designed production silicon, the AGI CPU, in March 2026 and identified TSMC as its manufacturer. This does not mean Arm fabricates every Arm-based chip.

Moore’s 1965 paper observed and projected rapidly increasing economically optimal component density. It was neither a law of nature nor a guarantee that performance must double on a fixed schedule. More transistors still meet memory latency, power density, and software parallelism limits, pushing designs toward caches, SIMD, out-of-order execution, multicore processors, and accelerators.

A CPU interprets instructions and advances complicated branches with an emphasis on latency. It also contains several forms of parallelism: pipelines, superscalar execution, branch prediction, SIMD, and multiple cores. A GPU groups many threads and hides waiting time with other work to raise throughput. A CPU core and a GPU execution unit are not comparable “cores.”

Performance also depends on where data lives—register, cache, main memory, VRAM, storage, or network—and how many bytes must move. Low-arithmetic-intensity work becomes bandwidth-bound, and transfer cost to a GPU can exceed the time saved. Bitcoin SHA-256 repeats regular integer operations over a small state and therefore occupies a different design region.

A benchmark needs the same application, input, precision, compiler, driver, memory capacity, wall-power boundary, and cooling conditions. Peak FLOPS is not application speed, while hashes per second is not floating-point performance. An institutional hardware record states which bottleneck a number actually measured.

Graphics accelerators and dedicated graphics processors existed before 1999. That year NVIDIA marketed the GeForce 256 as the “world’s first GPU” under its stated definition of a single-chip transform, lighting, triangle-setup, and rendering processor. Popularizing the GPU product category was consequential; it does not mean NVIDIA invented all graphics acceleration.

Programmable shaders helped general-purpose computing on GPUs move beyond graphics APIs. NVIDIA introduced CUDA in 2006, and Khronos released OpenCL 1.0 in 2008. In the common heterogeneous model, the CPU still controls flow, memory allocation, and kernel dispatch while the GPU executes highly parallel regions. The GPU is not an independent replacement for an entire application.

AMD’s graphics lineage includes ATI, acquired in 2006; today AMD designs CPUs, GPUs, and adaptive computing products. Intel also supplies integrated and discrete GPUs. Even if BOINC detects an NVIDIA, AMD, or Intel GPU, that device runs science only when the project provides a compatible application and the required driver environment.

An FPGA changes the configuration of logic blocks and interconnect in the field. Rather than merely stepping through software instructions, it can embody a purpose-built data path as a circuit. The Xilinx XC2064 in 1985 represents an early commercial FPGA. Design, synthesis, place-and-route, and timing closure are demanding, but the circuit remains updateable after manufacture—useful for prototypes, lower volumes, and low-latency pipelines.

An ASIC gives up that flexibility to remove unneeded instruction decoding and general resources, concentrating area, throughput, and energy on a narrow job. The tradeoffs are high design, verification, and mask costs; long lead times; and obsolescence when an algorithm changes. An ASIC is not simply a fast GPU, and an FPGA is not simply a slow ASIC. They fix decisions at different times.

Corporate attribution also needs dates. When Bitcoin FPGA miners appeared in 2011, Xilinx and Altera were independent companies. AMD acquired Xilinx in 2022. Intel acquired Altera in 2015, then sold a 51% interest to Silver Lake in September 2025 while retaining 49%. Later ownership does not retroactively own earlier inventions.

Sony, Toshiba, and IBM began jointly designing the Cell Broadband Engine (Cell/B.E.) at the STI Design Center in Austin in 2001. Its Power Architecture-based PPE controls the operating system, branching, and work assignment, while multiple SIMD-oriented SPEs use local stores and DMA for data-parallel kernels. The general Cell design contains eight SPEs, but scientific applications on PlayStation 3 could use six. A processor specification and the resources exposed by a product are not the same boundary.

Stanford University’s Folding@home and Sony Computer Entertainment released a PlayStation 3 client in March 2007. A PS3 connected to Folding@home’s own client-server infrastructure, received work contributing to molecular-dynamics trajectories for protein folding, misfolding, and related phenomena, computed it on Cell/B.E., and returned the output. Folding@home was not a BOINC project, and this was not an account of the PS3 RSX graphics processor doing the folding work. The compute engine was Cell/B.E.

A 2009 IPDPS paper reported roughly 50,000 active PS3s then contributing about 1,400 TFLOPS within a conservative estimate of roughly 4,800 TFLOPS for the whole Folding@home system using real application code. Sony’s 2008 CSR report separately recorded more than 1.4 million cumulative PS3 participants and the petaflop milestone. Registered or cumulative participants, concurrently active hosts, theoretical peak, and application throughput are different measurements.

The peer-reviewed Cell molecular-dynamics work showed how SIMD execution, local stores, and DMA could accelerate suitable simulation kernels, while also documenting limits from memory, data movement, and the narrow set of algorithms that mapped well. A PS3 was not a universal supercomputer. It materially expanded the research platform for suitable simulations, but no therapy or discovery should be attributed to PS3 alone. Trajectory analysis, hypothesis testing, reproduction, experiments, and review remain downstream steps.

The PS3 client ran until 6 November 2012. It was a time-bounded scientific instrument created by uniform consumer hardware, worldwide deployment, Sony’s distribution path, and Stanford’s research software. IBM and Toshiba were Cell co-designers; the direct Folding@home client collaboration was between the Stanford team and Sony Computer Entertainment. Chip design, console operation, and research-project stewardship remain separate contributions.

BOINC is middleware, not the scientific algorithm. It distributes project-specific applications across diverse hosts. A platform is broadly a processor architecture and operating-system combination; one research application may have CPU, GPU, OS-specific, and driver-specific versions. The scheduler uses plan classes and host data to judge compatibility, expected speed, CPU assistance, and accelerator type.

GPUGrid used CUDA in 2008, BOINC announced NVIDIA GPU support, and SETI@home released a CUDA application that December. This did not make every science workload faster on a GPU. Regular, high-arithmetic-intensity kernels accelerate well; branches, large memory, network I/O, porting cost, double precision, and short-lived research code can block a port. Keeping CPU versions is a workload and access decision, not technological backwardness.

Different hardware, compilers, and math libraries can change floating-point rounding and operation order. Correct CPU and GPU outputs may not be bit-identical, so projects use tolerances, application-specific validators, homogeneous redundancy, or comparison within the same application version. BOINC manages diversity through metadata and validation instead of pretending it does not exist.

NTT DATA’s cell computing Gene, released in 2005, contains “Cell” in its name but is unrelated to the Cell/B.E. processor. Gene combined BOINC, other open-source components, and NTT DATA software to distribute jobs across LAN PCs owned or managed by one organization. A shared word is not evidence that Gene and PS3/Folding@home belong to one hardware lineage.

Early Bitcoin clients contained a CPU miner, and an SSE2 SHA-256 optimization was shared in 2010. A public OpenCL GPU miner followed that year, open-source FPGA miners targeted Xilinx and Altera devices in 2011, and Canaan’s predecessor team records shipping Avalon ASIC machines in January 2013 in its SEC filing. These were overlapping transitions, not dates when every participant switched at once.

SHA-256d has a fixed input structure and operation sequence, repeatedly varying candidate block-header data to find a hash below the target. GPUs parallelized many trials, FPGAs expressed the hash pipeline in configurable logic, and ASICs fixed control and data paths around SHA-256. Because revenue maps directly to hash rate against electricity and capital costs, mining created a strong economic incentive for specialization.

Intel also announced its Blockscale SHA-256 ASIC in April 2022, listing up to 580 GH/s and up to 26 J/TH at the chip boundary—not for a complete miner or facility. In April 2023 Intel issued a product-discontinuance notice with a last-order date of October 20, 2023 and a forecast last-shipment date of April 20, 2024. The scale of an entrant and the persistence of its business are different facts.

The whitepaper’s “one-CPU-one-vote” is a historical expression for computing power, not a permanent rule assigning one vote to each x86 CPU. Chain selection compares cumulative proof of work. Neither the protocol nor a solo miner needs a central job server; a pool distributes jobs and measures lower-difficulty shares only when miners choose that arrangement. Full nodes trust no vendor and independently validate the block rules and proof of work.

BOINC credit, WCG points, runtime years, FLOPS, and Bitcoin hashes per second are not convertible. Scientific FLOPS cannot predict SHA-256 hash rate, and a miner’s TH/s does not rank scientific usefulness. Their common institutional outline is that participant-owned hardware, electricity, cooling, networking, and software can be coordinated into computation at planetary scale.

Intel designs x86 CPUs and other products and remains an integrated device manufacturer whose own fabs manufacture most of its products. AMD designs x86 CPUs, GPUs, and Xilinx-derived FPGA and adaptive products; NVIDIA designs GPUs and the CUDA software ecosystem. AMD and NVIDIA rely mainly on external foundries. TSMC is a pure-play foundry that manufactures customer designs—not a miner designer or pool operator.

A working system can require ISA and IP, architecture, RTL, EDA, wafer fabrication, memory, packaging, testing, boards, power supplies, firmware, cooling, networks, and facility operations. Arm centres on architecture and IP while expanding into Arm-designed silicon in 2026; ASML supplies lithography systems; companies such as Synopsys and Cadence supply EDA; TSMC, Samsung, and Intel fabricate wafers; and OSAT firms such as ASE assemble and test. “Semiconductor company” does not describe one role, nor does chip design imply ownership of the fab that manufactures it.

In Bitcoin ASICs, firms such as Canaan, Bitmain, and MicroBT design chips and integrate miner systems while contracting portions of fabrication, packaging, and testing. The protocol, firmware, mining pool, ASIC vendor, foundry, and operating facility remain distinct actors. In BOINC, Berkeley middleware, each research project, IBM or Krembil stewardship of WCG, volunteer hosts, and chip vendors likewise should not be merged into one company’s achievement.

ASIC J/TH can refer to at least three boundaries: a chip, a miner at the wall, or a facility. A chip figure excludes the power supply, fans, and controller; a miner figure excludes transformation, pumps, and building cooling. Temperature, voltage, frequency, firmware, overclocking, and utilization alter measurements. A product name alone is not an efficiency record.

In BOINC, “using idle hardware” does not make incremental electricity zero. The needed variables are marginal wall power over baseline, runtime, successful completion, retries, cooling, and location- and time-specific electricity. Credit, FLOPS, or aggregate runtime cannot by themselves yield kWh or carbon emissions.

Operational electricity must also be separated from lifecycle effects of wafer fabrication, packaging, transport, facility construction, and disposal. Better performance per watt does not ensure lower total electricity when network hash rate or participation grows. Efficiency, total consumption, carbon, and electronic waste are four different questions.

Every “first” needs three qualifiers: first at what, under which definition, and according to whom. Vendor timelines, product documents, and SEC filings are primary evidence of company action, but they also contain self-description. Pair them with museum collections, original papers, and source code so that marketing firsts and historical attribution remain distinct.

Do not assign achievements before an acquisition to the later parent. ATI’s graphics history joins AMD’s corporate history in 2006; Xilinx joins AMD in 2022. Supported operating systems, drivers, project status, and corporate ownership are living evidence with a lastVerified date; a 1945 report or 2013 paper is a fixed historical record.

Preserving a machine is more than displaying its enclosure. It means relating circuits, source, compilers, drivers, protocols, benchmark conditions, electricity boundaries, organizations, failed designs, and participant practice. Only then can we verify how desktop CPUs and GPUs became scientific instruments through SETI@home and BOINC, and how different conditions drove Bitcoin toward a specialized ASIC industry.